Semiconductor materials with narrow band gap, hereinafter referred to as III/V semiconductors, such as InAs and InSb, have high mobilities, high saturated carrier velocities and low contact resistances. This makes the materials good candidates for high-speed and low-power electronics, and over the recent years the interest in using these materials in a large variety of semiconductor devices has shown a significant increase. However, transistors made of these materials often suffer from poor current control, small current on/off ratios, strong thermal effects, and a large output conductance related to the narrow band gap. In addition, structures of III/V semiconductors should preferably, in order to be commercially interesting, be compatible with existing silicon based technology, for example be possible to fabricate on Si-substrates. This is, with conventional technology, difficult, due to the large lattice mismatch between Si and III/V semiconductor materials. These above mentioned effects limit the application areas of the III/V semiconductors devices and reduce the performance of analogue and digital applications. FIGS. 1a-c shows data for an InAs nanowire transistor, suffering from the above mentioned limitations: a) illustrates poor current control, b) the threshold control and c) the insufficient current on/off ratio.
In a typical planar Field Effect Transistor (FET) the source-drain current is confined to a planar layer of semiconductor material. This means that it is not possible to use heterostructures in the direction of the current path in the channel to improve the performance, as is done in vertical, for instance bipolar, transistors. It is also difficult to fabricate heterostructures with narrow bandgap materials: in III/V semiconductors due to the lack of suitable lattice matched materials and problems with Sb-based compounds, and for Ge, the large lattice mismatch to Si and SiC.
The growth of nanowires offers new possibilities in heterostructure design as radial strain relaxation allows a large range of new compositions to be fabricated. InP can, for example, be grown on InAs without defects as described by Samuelson et al., United States Patent Application US 2004/0075464 A1. It is also possible to use a substrate that is not lattice matched to the wires, which offers even more design flexibility and opens up a route to integrate III-V semiconductors on Si. Thus the above described problems can be mitigated by the use of devices of nanoscale dimensions.
Semiconductor nanowires is in this context defined as rod-shaped structures with a diameter less than 200 nm and a length up to several μm. The growth of semiconductor nanowires can be done in various ways, for example by Vapor Phase Epitaxi (VPE) using metal particles to assist the anisotropic growth as in the above referred US application to Samuelson et al.
In the nanowire geometry of the FET [Yazawa et al., U.S. Pat. No. 5,362,972] a nanowire field effect transistor is described. The gate surrounds the narrow nanowires providing good gate coupling and forming a wrap gate FET. The nanowires are homogenous GaAs whiskers grown by a vapour phase method.
The prior art nanowire transistor illustrates the potential of using the semiconductor nanowires. However, the experimental findings, for example with regards to Ion/Ioff, impact ionization rate etc, indicate that improvements are necessary before commercially attractive devices can be offered. Contacts to semiconductor devices is an area of special concern, as the contact resistance reduces speed and output power, but increases power consumption.